L
lzh08
Guest
bagaimana membangun dua port dual ram menggunakan M4K?
saya ingin menggunakan untuk membangun dua M4K dual port ram, masing-masing dual port ram 64k meliputi bit, total adalah 128K sedikit.
berikut adalah laporan setelah dikompilasi.
Total Memory bit: 65536/239216.
mengapa? i think hasilnya seharusnya 131072/239216.
bagaimana membangun dua port dual ram?
menggunakan "menghasilkan"?
--- kode
menggunakan IEEE.STD_LOGIC_1164.all;
menggunakan IEEE.STD_LOGIC_ARITH.all;
menggunakan IEEE.STD_LOGIC_UNSIGNED.all;
dualportram entitas adalah
pelabuhan
(
CLK: di std_logic;
dout: InOut std_logic_vector (7 downto 0)
)
dualportram akhir;
arsitektur tindakan dualportram adalah
komponen lpmramdp_1
PORT
(
Data: IN STD_LOGIC_VECTOR (15 downto 0);
wren: IN STD_LOGIC: = '1 ';
wraddress: IN STD_LOGIC_VECTOR (11 downto 0);
rdaddress: IN STD_LOGIC_VECTOR (12 downto 0);
Jam: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (7 downto 0)
)
komponen akhir;
komponen lpmramdp_2
PORT
(
Data: IN STD_LOGIC_VECTOR (15 downto 0);
wren: IN STD_LOGIC: = '1 ';
wraddress: IN STD_LOGIC_VECTOR (11 downto 0);
rdaddress: IN STD_LOGIC_VECTOR (12 downto 0);
Jam: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (7 downto 0)
)
komponen akhir;
sinyal wrCount_1: std_logic_vector (11 downto 0);
sinyal rdCount_1: std_logic_vector (12 downto 0);
sinyal dataIn_1: std_logic_vector (15 downto 0);
sinyal wrCount_2: std_logic_vector (11 downto 0);
sinyal rdCount_2: std_logic_vector (12 downto 0);
sinyal dataIn_2: std_logic_vector (15 downto 0);
- sinyal dataOut: std_logic_vector (7 downto 0);
mulai
proses (CLK)
mulai
jika rising_edge (CLK) lalu
wrCount_1 <= wrCount_1 1;
rdCount_1 <= rdCount_1 1;
wrCount_2 <= wrCount_2 1;
rdCount_2 <= rdCount_2 1;
end if;
proses akhir;
u1: lpmramdp_1
peta pelabuhan
(
data => dataIn_1,
wren => '1 ',
wraddress => wrCount_1,
rdaddress => rdCount_1,
Jam => CLK,
q => dout
)
u2: lpmramdp_2
peta pelabuhan
(
data => dataIn_2,
wren => '1 ',
wraddress => wrCount_2,
rdaddress => rdCount_2,
Jam => CLK,
q => dout
)
end;
saya ingin menggunakan untuk membangun dua M4K dual port ram, masing-masing dual port ram 64k meliputi bit, total adalah 128K sedikit.
berikut adalah laporan setelah dikompilasi.
Total Memory bit: 65536/239216.
mengapa? i think hasilnya seharusnya 131072/239216.
bagaimana membangun dua port dual ram?
menggunakan "menghasilkan"?
--- kode
menggunakan IEEE.STD_LOGIC_1164.all;
menggunakan IEEE.STD_LOGIC_ARITH.all;
menggunakan IEEE.STD_LOGIC_UNSIGNED.all;
dualportram entitas adalah
pelabuhan
(
CLK: di std_logic;
dout: InOut std_logic_vector (7 downto 0)
)
dualportram akhir;
arsitektur tindakan dualportram adalah
komponen lpmramdp_1
PORT
(
Data: IN STD_LOGIC_VECTOR (15 downto 0);
wren: IN STD_LOGIC: = '1 ';
wraddress: IN STD_LOGIC_VECTOR (11 downto 0);
rdaddress: IN STD_LOGIC_VECTOR (12 downto 0);
Jam: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (7 downto 0)
)
komponen akhir;
komponen lpmramdp_2
PORT
(
Data: IN STD_LOGIC_VECTOR (15 downto 0);
wren: IN STD_LOGIC: = '1 ';
wraddress: IN STD_LOGIC_VECTOR (11 downto 0);
rdaddress: IN STD_LOGIC_VECTOR (12 downto 0);
Jam: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (7 downto 0)
)
komponen akhir;
sinyal wrCount_1: std_logic_vector (11 downto 0);
sinyal rdCount_1: std_logic_vector (12 downto 0);
sinyal dataIn_1: std_logic_vector (15 downto 0);
sinyal wrCount_2: std_logic_vector (11 downto 0);
sinyal rdCount_2: std_logic_vector (12 downto 0);
sinyal dataIn_2: std_logic_vector (15 downto 0);
- sinyal dataOut: std_logic_vector (7 downto 0);
mulai
proses (CLK)
mulai
jika rising_edge (CLK) lalu
wrCount_1 <= wrCount_1 1;
rdCount_1 <= rdCount_1 1;
wrCount_2 <= wrCount_2 1;
rdCount_2 <= rdCount_2 1;
end if;
proses akhir;
u1: lpmramdp_1
peta pelabuhan
(
data => dataIn_1,
wren => '1 ',
wraddress => wrCount_1,
rdaddress => rdCount_1,
Jam => CLK,
q => dout
)
u2: lpmramdp_2
peta pelabuhan
(
data => dataIn_2,
wren => '1 ',
wraddress => wrCount_2,
rdaddress => rdCount_2,
Jam => CLK,
q => dout
)
end;